Table of Contents

Analog-to-Digital Converter (ADC)

24.1 Overview

24.1.1 Device-specific features

24.1.2 Device-specific pin configuration features

24.1.3 Device-specific implementation

24.2 Introduction

24.3 Functional description

24.3.1 Analog channel conversion

24.3.1.1 Normal conversion

24.3.1.2 Start of normal conversion

24.3.1.3 Normal conversion operating modes

Example 1. One Shot Mode (MODE = 0)

24.3.1.4 Injected channel conversion

24.3.1.5 Abort conversion

24.3.2 Analog clock generator and conversion timings

24.3.3 ADC sampling and conversion timing

24.3.4 ADC CTU (Cross Triggering Unit)

24.3.4.1 Overview

24.3.4.2 CTU in control mode

24.3.5 Programmable analog watchdog

24.3.5.1 Introduction

24.3.5.2 Analog watchdog functionality

24.3.6 DMA functionality

24.3.7 Interrupts

24.3.8 Power-down mode

24.3.9 Auto-clock-off mode

24.4 Register descriptions

24.4.1 Introduction

Offset from base address
ADC_0: 0xFFE0_0000
ADC_1: 0xFFE0_4000
Register name Location
0x0000 Main Configuration Register (MCR) on page 754
0x0004 Main Status Register (MSR) on page 755
0x0008–0x000F Reserved
0x0010 Interrupt Status Register (ISR) on page 757
0x0014–0x001F Reserved
0x0020 Interrupt Mask Register (IMR) on page 757
0x0024–0x002F Reserved
0x0030 Watchdog Threshold Interrupt Status Register (WTISR) on page 758
0x0034 Watchdog Threshold Interrupt Mask Register (WTIMR) on page 759
0x0038–0x003F Reserved
0x0040 DMA Enable Register (DMAE) on page 760
0x0044 DMA Channel Select Register 0 (DMAR0) on page 761
0x0048–0x004F Reserved
0x0050 Threshold Control Register 0 (TRC0) on page 762
0x0054 Threshold Control Register 1 (TRC1) on page 762
0x0058 Threshold Control Register 2 (TRC2) on page 762
0x005C Threshold Control Register 3 (TRC3) on page 762
0x0060 Threshold Register 0 (THRHLR0) on page 763
0x0064 Threshold Register 1 (THRHLR1) on page 763
0x0068 Threshold Register 2 (THRHLR2) on page 763
0x006C Threshold Register 3 (THRHLR3) on page 763
0x0070–0x0093 Reserved
0x0094 Conversion Timing Register 0 (CTR0) on page 764
0x0098–0x00A3 Reserved
0x00A4 Normal Conversion Mask Register 0 (NCMR0) on page 764
0x00A8–0x00B3 Reserved
0x00B4 Injected Conversion Mask Register 0 (JCMR0) on page 766
0x00B8–00C7 Reserved
0x00C8 Power-down Exit Delay Register (PDEDR) on page 767
0x00CC–0x00FF Reserved
0x0100 Channel 0 Data Register (CDR0) on page 767
0x0104 Channel 1 Data Register (CDR1) on page 767
0x0108 Channel 2 Data Register (CDR2) on page 767
0x010C Channel 3 Data Register (CDR3) on page 767
0x0110 Channel 4 Data Register (CDR4) on page 767
0x0114 Channel 5 Data Register (CDR5) on page 767
0x0118 Channel 6 Data Register (CDR6) on page 767
0x011C Channel 7 Data Register (CDR7) on page 767
0x0120 Channel 8 Data Register (CDR8) on page 767
0x0124 Channel 9 Data Register (CDR9) on page 767
0x0128 Channel 10 Data Register (CDR10) on page 767
0x012C Channel 11 Data Register (CDR11) on page 767
0x0130 Channel 12 Data Register (CDR12) on page 767
0x0134 Channel 13 Data Register (CDR13) on page 767
0x0138 Channel 14 Data Register (CDR14) on page 767
0x013C Channel 15 Data Register (CDR15)
available only on ADC_0
on page 767

24.4.2 Control logic registers

24.4.2.1 Main Configuration Register (MCR)

Field Description
OWREN Overwrite enable
This bit enables or disables the functionality to overwrite unread converted data.
0 Prevents overwrite of unread converted data; new result is discarded
1 Enables converted data to be overwritten by a new conversion
WLSIDE Write left/right-aligned
0 The conversion data is written right-aligned.
1 Data is left-aligned (from 15 to (15 – resolution + 1)).
The WLSIDE bit affects all the CDR registers simultaneously. See Figure 460 and Figure 460.
MODE One Shot/Scan
0 One Shot Mode—Configures the normal conversion of one chain.
1 Scan Mode—Configures continuous chain conversion mode; when the programmed chain
conversion is finished it restarts immediately.
NSTART Normal Start conversion
Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes the current chain conversion to finish, then stops the operation.
This bit stays high while the conversion is ongoing (or pending during injection mode).
0 Causes the current chain conversion to finish and stops the operation
1 Starts the chain or scan conversion
JTRGEN Injection external trigger enable
0 External trigger disabled for channel injection
1 External trigger enabled for channel injection
JEDGE Injection trigger edge selection
Edge selection for external trigger, if JTRGEN = 1.
0 Selects falling edge for the external trigger
1 Selects rising edge for the external trigger
JSTART Injection start
Setting this bit will start the configured injected analog channels to be converted by software.
Resetting this bit has no effect, as the injected chain conversion cannot be interrupted.
CTUEN Cross trigger unit conversion enable
0 CTU triggered conversion disabled
1 CTU triggered conversion enabled
ADCLKSEL Analog clock select
This bit can only be written when ADC in Power-Down mode
0 ADC clock frequency is half Peripheral Set Clock frequency
1 ADC clock frequency is equal to Peripheral Set Clock frequency
ABORTCHAIN Abort Chain
When this bit is set, the ongoing Chain Conversion is aborted. This bit is reset by hardware as soon as a new conversion is requested.
0 Conversion is not affected
1 Aborts the ongoing chain conversion
ABORT Abort Conversion
When this bit is set, the ongoing conversion is aborted and a new conversion is invoked. This bit is reset by hardware as soon as a new conversion is invoked. If it is set during a scan chain, only the ongoing conversion is aborted and the next conversion is performed as planned.
0 Conversion is not affected
1 Aborts the ongoing conversion
ACKO Auto-clock-off enable
If set, this bit enables the Auto clock off feature.
0 Auto clock off disabled
1 Auto clock off enabled
PWDN Power-down enable
When this bit is set, the analog module is requested to enter Power Down mode. When ADC status is PWDN, resetting this bit starts ADC transition to IDLE mode.
0 ADC is in normal mode
1 ADC has been requested to power down

24.4.2.2 Main Status Register (MSR)

Field Description
NSTART This status bit is used to signal that a Normal conversion is ongoing.
JABORT This status bit is used to signal that an Injected conversion has been aborted. This bit is reset when a new injected conversion starts.
JSTART This status bit is used to signal that an Injected conversion is ongoing.
CTUSTART This status bit is used to signal that a CTU conversion is ongoing.
CHADDR Current conversion channel address
This status field indicates current conversion channel address.
ACKO Auto-clock-off enable
This status bit is used to signal if the Auto-clock-off feature is on.
ADCSTATUS The value of this parameter depends on ADC status:
000 IDLE — The ADC is powered up but idle.
001 Power-down — The ADC is powered down.
010 Wait state — The ADC is waiting for an external multiplexer. This occurs only when the DSDR register is non-zero.
011 Reserved
100 Sample — The ADC is sampling the analog signal.
101 Reserved
110 Conversion — The ADC is converting the sampled signal.
111 Reserved

24.4.3 Interrupt registers

24.4.3.1 Interrupt Status Register (ISR)

24.4.3.2 Interrupt Mask Register (IMR)

24.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR)

24.4.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR)

24.4.4 DMA registers

24.4.4.1 DMA Enable (DMAE) register

24.4.4.2 DMA Channel Select Register (DMAR[0])

24.4.5 Threshold registers

24.4.5.1 Introduction

24.4.5.2 Threshold Control Register (TRCx, x = [0..3])

24.4.5.3 Threshold Register (THRHLR[0:3])

24.4.6 Conversion Timing Registers CTR[0]

Field Description
INPLATCH Configuration bit for latching phase duration
OFFSHIFT Configuration for offset shift characteristic
00 No shift (that is the transition between codes 000h and 001h) is reached when the AVIN (analog input voltage) is equal to 1 LSB.
01 Transition between code 000h and 001h is reached when the AVIN is equal to1/2 LSB
10 Transition between code 00h and 001h is reached when the AVIN is equal to 0
11 Not used
Note: Available only on CTR0
INPCMP Configuration bits for comparison phase duration
INPSAMP Configuration bits for sampling phase duration

24.4.7 Mask registers

24.4.7.1 Introduction

24.4.7.2 Normal Conversion Mask Registers (NCMR[0])

Field Description
CHn Sampling enable
When set Sampling is enabled for channel n.

24.4.7.3 Injected Conversion Mask Registers (JCMR[0])

Field Description
CHn Sampling enable
When set, sampling is enabled for channel n

24.4.8 Delay registers

24.4.8.1 Power-Down Exit Delay Register (PDEDR)

24.4.9 Data registers

24.4.9.1 Introduction

24.4.9.2 Channel Data Registers (CDR[0..15])

Field Description
VALID Used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read.
OVERW Overwrite data
This bit signals that the previous converted data has been overwritten by a new conversion. This functionality depends on the value of MCR[OWREN]:
– When OWREN = 0, then OVERW is frozen to 0 and CDATA field is protected against being overwritten until being read.
– When OWREN = 1, then OVERW flags the CDATA field overwrite status.
0 Converted data has not been overwritten
1 Previous converted data has been overwritten before having been read
RESULT This bit reflects the mode of conversion for the corresponding channel.
00 Data is a result of Normal conversion mode
01 Data is a result of Injected conversion mode
10 Data is a result of CTU conversion mode
11 Reserved
CDATA Channel 0-15 converted data. Depending on the value of the MCR[WLSIDE] bit, the position of this field can be changed as shown in Figure 460.

Back