• Based on Chapter 24

• 2 ADC units
  • 26 input channels (2 × 11 plus 4 shared)
  • ADC_0: channel 15 dedicated for the internal 1.2 V rail
  • Channels 11 to 14 shared between the two converters
• 10-bit resolution
• Conversion time < 1 µs including sampling time at full precision (conversion time target of 700 ns for the analog section)
• Cross triggering unit (CTU)
• 4 analog watchdogs with interrupt capability for continuous hardware monitoring of as many as 4 analog input channels
• Clock stretching (with CTU pulse)
• Sampling and conversion time register CTR0 (internal precision channels)
• Left-aligned result format
• Right-aligned result format
• One Shot/Scan Modes
• Chain Injection Mode
• Power-down mode
• 2 different Abort functions allow aborting either single-channel conversion or chain conversion
• As many as 16 data registers for storing converted data. Conversion information, such as mode of operation (normal, injected or CTU), is associated to data value.
• Auto-clock-off
• 2 modes of operation, each with DMA compatible interface
  • Normal Mode
  • CTU Control Mode
• These features are absent on the device:
  • Support of external channels
  • Presampling
  • Alternate analog thresholds
  • Offset Cancellation and Offset Refresh Control
  • External start and triggering

• For Section 24.3.3, ADC sampling and conversion timing,” fck = (1/2) MC_PLL_CLK is true where the bit ADCLKSEL would be always 0 (default value), meaning that AD_clk is half of MC_PLL_CLK. A clock prescaler (1 or 2) can be configured. The AD_clk has the same frequency of MC_PLL_CLK or is half of MC_PLL_CLK, depending on the value of the bit ADCLKSEL.
• CTUEN field in the MCR: Enables or disables CTU control mode
• Registers CDR[16..95] not used

• 
  Figure 440. ADC implementation

• The analog-to-digital converter (ADC) block provides accurate and fast conversions for a wide range of applications.
• The ADC contains advanced features for normal or injected conversion. It provides support for eDMA (direct memory access) mode operation. A conversion can be triggered by software or hardware (Cross Triggering Unit or PIT).
• The mask registers present within the ADC can be programmed to configure the channel to be converted.
• A conversion timing register for configuring different sampling and conversion times is associated to each channel type.
• Analog watchdogs allow continuous hardware monitoring.

• Two conversion modes are available within the ADC:
  • Normal conversion
  • Injected conversion

• This is the normal conversion that the user programs by configuring the normal conversion mask registers (NCMR). Each channel can be individually enabled by setting ‘1’ in the corresponding field of NCMR registers. Mask registers must be programmed before starting the conversion and cannot be changed until the conversion of all the selected channels ends (NSTART bit in the Main Status Register (MSR) is reset).

• By programming the configuration bits in the Main Configuration Register (MCR), the normal conversion can be started in two ways:
  • By software — The conversion chain starts when the MCR[NSTART] bit is set.
  • By trigger — An on-chip internal signal triggers an ADC conversion. The settings in the MCR select how conversions are triggered based on these internal signals:
    • A rising/falling edge detected in the signal sets the MSR[NSTART] bit and starts the programmed conversion.
    • The conversion is started if and only if the MCR[NSTART] bit is set and the programmed level on the trigger signal is detected.
• Table 421. Configurations for starting normal conversion
  
• The MSR[NSTART] status bit is automatically set when the normal conversion starts. At the same time the MCR[NSTART] bit is reset, allowing the software to program a new start of conversion. In that case the new requested conversion starts after the running conversion is completed.
• If the content of all the normal conversion mask registers is zero (that is, no channel is selected) the conversion operation is considered completed and the interrupt ECH (see interrupt controller chapter for further details) is immediately issued after the start of conversion

• Two operating modes are available for the normal conversion:
  • One Shot
  • Scan
• To enter one of these modes, it is necessary to program the MCR[MODE] bit. The first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is converted to digital as shown in Figure 441.
• 
  Figure 441. Normal conversion flow
• In One Shot Mode (MODE = 0) a sequential conversion specified in the NCMR registers is performed only once. At the end of each conversion, the digital result of the conversion is stored in the corresponding data register.

• Channels A-B-C-D-E-F-G-H are present in the device where channels B-D-E are to be converted in the One Shot Mode. MODE = 0 is set for One Shot mode. Conversion starts from the channel B followed by conversion of channels D-E. At the end of conversion of channel E the scanning of channels stops.
• The NSTART status bit in the MSR is automatically set when the Normal conversion starts. At the same time the MCR[NSTART] bit is reset, allowing the software to program a new start of conversion. In that case the new requested conversion starts after the running conversion is completed.
• In Scan Mode (MODE = 1), a sequential conversion of N channels specified in the NCMR registers is continuously performed. As in the previous case, at the end of each conversion the digital result of the conversion is stored into the corresponding data register.
• The MSR[NSTART] status bit is automatically set when the Normal conversion starts. Unlike One Shot Mode, the MCR[NSTART] bit is not reset. It can be reset by software when the user needs to stop scan mode. In that case, the ADC completes the current scan conversion and, after the last conversion, also resets the MSR[NSTART] bit.
• Channels A-B-C-D-E-F-G-H are present in the device where channels B-D-E are to be converted in the Scan Mode. MODE = 1 is set for Scan Mode. Conversion starts from the channel B followed by conversion of the channels D-E. At the end of conversion of channel E the scanning of channel B starts followed by conversion of the channels D-E. This sequence repeats itself till the MCR[NSTART] bit is cleared by software.
• At the end of each conversion an End Of Conversion interrupt is issued (if enabled by the corresponding mask bit) and at the end of the conversion sequence an End Of Chain interrupt is issued (if enabled by the corresponding mask bit in the IMR register).

• A conversion chain can be injected into the ongoing normal conversion by configuring the Injected Conversion Mask Registers (JCMR). As with normal conversion, each channel can be selected individually. This injected conversion (which can occur only in One Shot mode) interrupts the normal conversion (which can be in One Shot or Scan mode). When an injected conversion is inserted, ongoing normal channel conversion is aborted and the injected channel request is processed. After the last channel in the injected chain is converted, normal conversion resumes from the channel at which the normal conversion was aborted, as shown in Figure 442.
• 
  Figure 442. Injected sample/conversion sequence
• The injected conversion can be started using two options:
  • By software setting the MCR[JSTART]; the current conversion is suspended and the injected chain is converted. At the end of the chain, the JSTART bit in the MSR is reset and the normal chain conversion is resumed.
  • By an internal trigger signal from the PIT when MCR[JTRGEN] is set; a programmed event (rising/falling edge depending on MCR[JEDGE]) on the signal coming from PIT or CTU starts the injected conversion by setting the MSR[JSTART]. At the end of the chain, the MSR[JSTART] is cleared and the normal conversion chain is resumed.
• The MSR[JSTART] is automatically set when the Injected conversion starts. At the same time the MCR[JSTART] is reset, allowing the software to program a new start of conversion. In that case the new requested conversion starts after the running injected conversion is completed.
• At the end of each injected conversion, an End Of Injected Conversion (JEOC) interrupt is issued (if enabled by the IMR[MSKJEOC]) and at the end of the sequence an End Of Injected Chain (JECH) interrupt is issued (if enabled by the IMR[MSKJEOC]).
• If the content of all the injected conversion mask registers (JCMR) is zero (that is, no channel is selected) the JECH interrupt is immediately issued after the start of conversion.
• Once started, injected chain conversion cannot be interrupted by any other conversion type (it can, however, be aborted; see Section 24.3.1.5, Abort conversion).

• Two different abort functions are provided.
  • The user can abort the ongoing conversion by setting the MCR[ABORT] bit. The current conversion is aborted and the conversion of the next channel of the chain is immediately started. In the case of an abort operation, the NSTART/JSTART bit remains set and the ABORT bit is reset after the conversion of the next channel starts. The EOC interrupt corresponding to the aborted channel is not generated. This behavior is true for normal or triggered/Injected conversion modes. If the last channel of a chain is aborted, the end of chain is reported generating an ECH interrupt.
  • It is also possible to abort the current chain conversion by setting the MCR[ABORTCHAIN] bit. In that case the behavior of the ADC depends on the MODE bit. If scan mode is disabled, the NSTART bit is automatically reset together with the MCR[ABORTCHAIN] bit. Otherwise, if the scan mode is enabled, a new chain conversion is started. The EOC interrupt of the current aborted conversion is not generated but an ECH interrupt is generated to signal the end of the chain. When a chain conversion abort is requested (ABORTCHAIN bit is set) while an injected conversion is running over a suspended Normal conversion, both injected chain and Normal conversion chain are aborted (both the NSTART and JSTART bits are also reset).

• The clock frequency can be selected by programming the MCR[ADCLKSEL]. When this bit is set to ‘1’ the ADC clock has the same frequency as the MC_PLL_CLK. Otherwise, the ADC clock is half of the MC_PLL_CLK frequency. The ADCLKSEL bit can be written only in power-down mode.
• When the internal divider is not enabled (ADCCLKSEL = 1), it is important that the associated clock divider in the clock generation module is ‘1’. This is needed to ensure 50% clock duty cycle.
• The direct clock should basically be used only in low power mode when the device is using only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock (an 8 MHz clock is not fast enough).
• In all other cases, the ADC should use the clock divided by two internally.
• Depending on the position of the rising edge of the signal internal trigger signal coming from the CTU, the ADC clock could also be stretched as illustrated in Figure 443.
• 
  Figure 443. Prescaler simplified block diagram
• The clock stretching is implemented if and only if ADCLKSEL = 0 (and clock is half of the MC_PLL_CLK).

• In order to support different loading and switching times, several different Conversion Timing registers (CTR) are present. There is one register per channel type. INPLATCH and INPCMP configurations are limited when the system clock frequency is greater than 20 MHz.
• When a conversion is started, the ADC connects the internal sampling capacitor to the respective analog input pin, allowing the capacitance to charge up to the input voltage value. The time to load the capacitor is referred to as sampling time. After completion of the sampling phase, the evaluation phase starts and all the bits corresponding to the resolution of the ADC are estimated to provide the conversion result.
• The conversion times are programmed via the bit fields of the CTR. Bit fields INPLATCH, INPCMP, and INPSAMP define the total conversion duration (Tconv) and in particular the partition between sampling phase duration (Tsample) and total evaluation phase duration (Teval).
• Figure 444 represents the sampling and conversion sequence.
• 
  Note: Operating conditions — INPLATCH = 0, INPSAMP = 3, INPCMP = 1 and Fadc clk = 20 MHz
  Figure 444. Sampling and conversion timings
• In the following equation, the unit Tck refers to the reciprocal of the motor control clock which is then modified by value of the MCR.ADCCLKSEL field:
• 
• The sampling phase duration is:
• 
• INPSAMPLES must be greater or equal to 8 (hardware requirement). If INPSAMPLES is < 3, the sampling time remains as if INPSAMPLES = 3.
• nDELAY = 0.5 if INPSAMPLES ⇐ 6, = 1 otherwise
• The total evaluation phase duration is:
• 
• INPCMP must be greater than or equal to 1 and INPLATCH must be less than INCMP (hardware requirements).
• Table 422. Relation between INPCMP and Tbiteval
  
• NOTE:
  • 1. The Tsample and Teval must respect the minimum value specified in the Data Sheet to allow ADC to reach TUE performance.
  • 2. For Tbiteval/INPCMP explanation, please refer to Table 422 (Relation between INPCMP and Tbiteval).
• The total conversion duration Tconv is (not including external multiplexing) the time to perform the total evaluation:
• 
• where
• 
• Table 423. Relation between MCR.CTUEN, MCR.ADCCLKSEL, and TCTUSYNC
  
• Table 424. Max/Min ADC_clk frequency and related configuration settings at 5 V / 3.3 V
  

• Table 425. ADC sampling and conversion timing at 5 V / 3.3 V
  

• The ADC cross triggering unit (CTU) is added to enhance the injected conversion capability of the ADC. The CTU contains multiple event inputs that can be used to select the channels to be converted from the appropriate event configuration register. The CTU generates a trigger output pulse of one clock cycle and outputs onto an internal data bus the channel to be converted. A single channel is converted for each request. After performing the conversion, the ADC returns the result on internal bus. The conversion result is also saved in the corresponding data register and it is compared with watchdog thresholds if requested. The CTU can be enabled by setting MCR[CTUEN].
• The CTU and the ADC are synchronous with the MC_PLL_CLK in both cases.

• In CTU control mode, the CPU is able to write in the ADC registers but it cannot start any conversion.
• Conversion requests can be generated only by the CTU trigger pulse. If a normal or injected conversion is requested, it is automatically discarded.
• When a CTU trigger pulse is received with the injected channel number, the conversion starts. The CTUSTART bit is set automatically at this point and it is also automatically reset when CTU Control mode is disabled (CTUEN = ‘0’).

• The analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in Figure 445) specified by an upper and a lower threshold value named THRH and THRL respectively.
• 
  Figure 445. Guarded area
• After the conversion of the selected channel, a comparison is performed between the converted value and the threshold values. If the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. The comparison result is stored as WTISR[WDGxH] and WTISR[WDGxL] as explained in Table 426. Depending on the mask bits WTIMR[MSKWDGxL] and WTIMR[MSKWDGxH], an interrupt is generated on threshold violation.
• Table 426. Values of WDGxH and WDGxL fields
  
• The TRC[THRCH] field specifies the channel on which the analog watchdog is applied. The analog watchdog is enabled by setting the corresponding TRC[THREN].
• The lower and higher threshold values for the analog watchdog are programmed using the THRHLR registers.
• For example, if channel number 3 is to be monitored with threshold values in THRHLR1, then the TRC[THRCH] field is programmed to select channel number 3.
• A set of threshold registers (THRHLRx and TRCx) can be linked only to a single channel for a particular THRCH value. If another channel is to be monitored with same threshold values, then the TRCx[THRCH] must be programmed again.
• NOTE
  • If the higher threshold for the analog watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the WDGxL interrupt for the low threshold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher threshold) then the interrupt WDGxH for high threshold violation is set. Thus, the user should avoid that situation as it could lead to misinterpretation of the watchdog interrupts.

• For each input channel the result of the comparison is reflected in the THROP bit in TRC register based on the converted analog values received by the analog watchdogs:
  • If the converted data value is lower than the lower threshold then the THROP bit in TRC register will be set to 1.
  • If the converted voltage is higher than the higher threshold then the THROP bit in TRC register will be set to 0.
  • If the converted voltage lies between the upper and the lower threshold guard window then THROP bit in TRC register will keep its logic value.
• The logic level of the THROP bit can be programmed by software. In fact, the user can decide to keep the behavior described or to invert the output logic level by setting the THRINV bit in the TRC register.
• An example of the operation is shown in Table 427.
• Table 427. Example for Analog watchdog operation
  

• A DMA request can be programmed after the conversion of every channel by setting the respective masking bit in the DMAR registers. The DMAR masking registers must be programmed before starting any conversion. There is one DMAR per channel type.
• The DMA transfers can be enabled using the DMAEN bit of DMAE register. When the DCLR bit of DMAE register is set, the DMA request is cleared the register enabled for DMA transfer has been read.

• The ADC generates the following maskable interrupt signals:
  • EOC (end of conversion) interrupt request
  • ECH (end of chain) interrupt request
  • JEOC (end of injected conversion) interrupt request
  • JECH (end of injected chain) interrupt request
  • EOCTU (end of CTU conversion) interrupt request
  • WDGxL and WDGxH (watchdog threshold) interrupt requests
• Interrupts are generated during the conversion process to signal events such as End Of Conversion as explained in register description for ISR and IMR.
• The analog watchdog interrupts are handled by two registers WTISR (Watchdog Threshold Interrupt Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in order to check and enable the interrupt request to the INTC module. The Watchdog interrupt source sets two pending bits WDGxH and WDGxL in the WTISR for each of the channels being monitored.

• The analog part of the ADC can be put in low power mode by setting the MCR[PWDN]. After releasing the reset signal the ADC analog module is kept in power-down mode by default, so this state must be exited before starting any operation by resetting the appropriate bit in the MCR.
• The power-down mode can be requested at any time by setting the MCR[PWDN]. If a conversion is ongoing, the ADC must complete the conversion before entering the power down mode. In fact, the ADC enters power-down mode only after completing the ongoing conversion. Otherwise, the ongoing operation should be aborted manually by resetting the NSTART bit and using the ABORTCHAIN bit.
• MSR[ADCSTATUS] bit is set only when ADC enters power-down mode.
• After the power-down phase is completed the process ongoing before the power-down phase must be restarted manually by setting the appropriate MCR[START] bit.
• Resetting MCR[PWDN] bit and setting MCR[NSTART] or MCR[JSTART] bit during the same cycle is forbidden.
• If a CTU trigger pulse is received during power-down, it is discarded.
• If the CTU is enabled and the MSR[CTUSTART] bit is ‘1’, then the MCR[PWDN] bit cannot be set.

• To reduce power consumption during the IDLE mode of operation (without going into power-down mode), an “auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit. When enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed by the user.
• NOTE
  • The auto-clock-off feature cannot operate when the digital interface runs at the same rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock will not shut down in IDLE mode.

• Table 428 lists ADC registers with their address offsets and reset values.
• Table 428. ADC digital registers

• The Main Configuration Register (MCR) provides configuration settings for the ADC.
• 
• Table 429. MCR field descriptions

• The Main Status Register (MSR) provides status bits for the ADC.
• 
  Figure 447. Main Status Register (MSR)
• Table 430. MSR field descriptions

• NOTE
  • MSR[JSTART] is automatically set when the injected conversion starts. At the same time MCR[JSTART] is reset, allowing the software to program a new start of conversion.
  • The JCMR registers do not change their values.

• CTR0 = associated to internal precision channels (from 0 to 15)
• 

• The Mask registers are used to program the 16 input channels that are converted during Normal and Injected conversion.

• NCMR0 = Enable bits of normal sampling for channel 0 to 15 (precision channels)
• 
• Table 440. NCMR field descriptions

• JCMR0 = Enable bits of injected sampling for channel 0 to 15 (precision channels)
• 
• Table 441. JCMR field descriptions

• CDR[0..15] = precision channels
• Each data register also gives information regarding the corresponding result as described below.
• 
• Table 443. CDR field descriptions

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