• Launch Libero
  • 
• Select [Project] → [New Project]
  • Named: [FirstTestProject]
  • HDL Language: [verilog]
  • 
  • 
• Select [M1A3P250-VQ100]
  • 
• I/O Setting: [LVCMOS 3.3V]
  • 
• Since now we have no HDL file yet, select [Next]
  • 
• We have no constriant frile yet, select [Finish]
  • 
• No, Enter the main window
  • 
• [File] → [New] - > [SmartDesign]
  • 
  • 
• Then, enter the main window
  • 

• Select [Catalog] → [Clock & Management] → [PLL - Static]
  • 
• CLK A Setting set as: [40] MHz
  • 
• Primary GLA set as: [4] MHz and checked the [Lock Control]
  • 
• Then, Select [Generate…]
  • 
• Core Name set as [PLL40_4] & Select [OK]
  • 
• Back to main windows, there is a new block in top smart design windows as shown as follows:
  • 

• From [Catalog] → Search [Counter]
• Select the [Counter]
  • 
• Set the counter properites, Async Cleae set as [Active Low], [26] bits width counter, then Select [Generate…]
  • 
• Core name set as [Counter], and press [OK]
  • 
• Back to main widow, the Counter_0 is shown as follows:
  • 

• [File] → [New] → [HDL]
  • 
• Create a [Verilog] → Name: [DeMux]
  • 
• Then, the DeMux was been created as follows:
  • 
• Rewrite the DeMux.v as follows:

  ///////////////////////////////////////////////////////////////////////////////////////////////////
  // Company: <Name>
  //
  // File: DeMux.v
  // File history:
  //      <Revision number>: <Date>: <Comments>
  //      <Revision number>: <Date>: <Comments>
  //      <Revision number>: <Date>: <Comments>
  //
  // Description: 
  //
  // <Description here>
  //
  // Targeted device: <Family::ProASIC3> <Die::M1A3P250> <Package::100 VQFP>
  // Author: <Name>
  //
  /////////////////////////////////////////////////////////////////////////////////////////////////// 
  
  //`timescale <time_units> / <precision>
  
  module DeMux( a_in, sel, y_out );
  input a_in;
  input [1:0] sel;
  output reg [3:0] y_out;
  
  //<statements>
  always @(a_in, sel)
  begin
      case (sel)
          2'b00: begin 
                  y_out[0]=a_in; y_out[1]=1'b0; y_out[2]=1'b0; y_out[3]= 1'b0; 
                 end
          2'b01: begin 
                  y_out[0]=1'b0; y_out[1]=a_in; y_out[2]=1'b0; y_out[3]=1'b0; 
                 end
          2'b10: begin 
                  y_out[0]=1'b0; y_out[1]=1'b0; y_out[2]=a_in; y_out[3]=1'b0; 
                 end
          2'b11: begin 
                  y_out[0]=1'b0; y_out[1]=1'b0; y_out[2]=1'b0; y_out[3]=a_in; 
                 end
          default: y_out=4'b0000;
      endcase
  end
  
  endmodule

  • 
• After stored the file. we can use the right-click menu of Ctrl-B to check the syntax of the Verilog code.
  • 
  • 
• Then, we can drag the DeMux.v into SmartDesign Window
  • 

• We can press the [Ctrl] key and select the pin that we need connect together
  • 
• Use the mouse right click menu, select [Connect]
  • 
• Then, the net will be created.
  • 
• We need, slice the bits, select the signal and use mouse right-click menu, select [Edit Slice…]
  • 
• We can separate the bits that we need.
  • 
• The block will seperates the signals.
  • 
• Wiring the related wires as follows:
  • 
• For those unwired signal, we can mark it as [Make Unused]
  • 
  • 
• The PowerDown Signal, we can set as [Tie High] for pull-up.
  • 
  • 
• The top level signals, we can set them as [Promote to Top Level]
  • 
  • 

• Goto [Design] → [Synthesize], use mouse right button menu, select [Run]
  • 
• Oops, I am facing the [FlexNet Licensing Error Issue]
  • 
• Let me check with FAE and then will back to finish this project.
• After the license issue resolved, we can synthesize and compile this project
  • 
  • 

• 359 person(s) visited this page until now.

Back