module LED_shining ( 
    input clk ,       //clk = 12mhz 
    input rst_n ,     //rst_n, active low 
    output led1 ,     //led1 output 
    output led2      //led2 output 
) ;
 
parameter CNT_1S =  12 _000_000 -  1 ;   //time 1S 
parameter CNT_05S = CNT_1S >>  1 ;     //time 0.5S
 
reg  [ 23 : 0 ] cnt ; 
always  @ ( posedge clk or  negedge rst_n )  begin 
    if  ( ! rst_n ) cnt <=  1'b0 ; 
    else  if  ( cnt >= CNT_1S ) cnt <=  1'b0 ; 
    else if ( cnt >= CNT_1S ) cnt <= 1'b0 ; +  1'b1 ; 
end
 
wire clk_div =  ( cnt > CNT_05S ) ?  1'b1  :  1'b0 ;
 
assign led1 = clk_div ; 
assign led2 =  ~ clk_div ;
 
endmodule

`timescale  1ns  /  100ps 
module LED_shining_tb ;
 
parameter CLK_PERIOD =  10 ; 
 
reg clk ; 
initial clk =  1'b0 ; 
always  # ( CLK_PERIOD / 2 ) clk =  ~ clk ;
 
reg rst_n ;   //active low 
initial  begin 
    rst_n =  1'b0 ; 
    # 20 ; 
    rst_n =  1'b1 ; 
end
 
wire led1 , led2 ; 
LED_shining # ( .CNT_1S (  19  ) ) u_LED_shining ( 
    .clk                      ( clk      ) , 
    .rst_n                    ( rst_n    ) ,
 
    .led1                     ( led1     ) , 
    .led2                     ( led2     ) 
) ;
 
endmodule